• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    The present invention relates to a flash memory device and a program, erase and read method using the same, and reduces the area occupied by contact holes by sharing four source or drain regions of four memory cells on a silicon substrate having a triple well structure. In addition, by increasing the size of the floating gate, there is an effect of improving the integration degree and operation characteristics of the device.
    公开号:KR19980055726A
    申请号:KR1019960074962
    申请日:1996-12-28
    公开日:1998-09-25
    发明作者:강호철；김종오
    申请人:김영환；현대전자산업 주식회사；
    IPC主号:
    专利说明:

    Flash memory device and program, erase and read method using same
    The present invention relates to a flash memory device and a program, erase and read method using the same. In particular, four memory cells can share a single source region or a drain region in order to improve the integration density of a stacked flash EPIROM. One flash memory device and a program, erase and read method using the same.
    In general, a flash memory device having electrical program and erase functions is composed of a peripheral circuit and a memory cell array. The memory cell array is composed of a plurality of memory cells each selected by a word line and a bit line signal. A program operation for storing data in the memory cell is a floating gate. This is done by allowing hot electrons to be injected into the gate. The erase operation for erasing the stored information is performed by causing the electrons injected into the floating gate to be discharged. Also, such a memory cell is classified into a stack gate type and a split gate type according to the shape of a gate electrode. A flash memory device including a stacked gate type memory cell is illustrated in FIG. 1.
    In the conventional stacked gate type memory cell, the field oxide film 1 is formed in the device isolation region of the silicon substrate, and the silicon substrate and the floating gate are electrically separated by the tunnel oxide layer on the channel region of the silicon substrate. The floating gate 2 is formed to partially overlap the upper end and the lower end of the field oxide film 1. And a control gate 3 electrically separated from the floating gate 2 by a dielectric film is formed on the top including the field oxide film 1 and the floating gate 2 formed in a direction crossing the field oxide film 1. do. In addition, a drain region 6 is formed in the silicon substrate inside the control gate 3 intersecting with both sides of the field oxide film 1, and the outside of the control gate 3 intersecting with both sides of the field oxide film 1, respectively. The source region 5 is formed in the silicon substrate. In the drain region 6, a contact portion 4 for connecting to a bit line formed to intersect the control gate 3 is formed.
    In the flash memory device configured as described above, two bits Bit, that is, a contact formed in the contact portion 4 of the drain region 6 commonly connected to the drain regions 6 of the two memory cells are commonly connected. The drain region 6 is connected to the bit line through the hole. However, since the size of the device is determined by the size of the contact hole and the area occupied by the contact hole, it is difficult to improve the integration of the device when using the layout as described above, and the control gate 3, the contact part 4, and the contact part are difficult to improve. A problem arises in that it is difficult to properly maintain the distance between (4) and the field oxide film 1.
    Accordingly, the present invention provides a flash memory device in which four memory cells can share one source region or drain region on a silicon substrate having a triple well structure, and a program, erase, and read method using the same. For the purpose of
    The flash memory device according to the present invention for realizing the above object is formed on a silicon substrate having a triple well structure, a field oxide film formed in each device isolation region of the silicon substrate, and a field oxide film adjacent to each other. A floating gate is formed to have the same width as that of the floating gate, including a floating gate formed to partially overlap the field oxide layer and electrically separated from the silicon substrate by a tunnel oxide layer, and the floating gate formed adjacent to the horizontal direction. A control gate formed so as to be electrically separated from the floating gate, a source region formed on the silicon substrate in a portion surrounded by the four adjacent field oxide films and the floating gate, and having a source contact portion, and adjacent to the source region. The floating It formed in the silicon substrate adjacent to the other one side of the site is composed of a drain region having a drain contact.
    In order to achieve the above object, a program method of a flash memory device according to the present invention first applies a voltage of V PG (8 to 20 V) to a word line selected for programming data in a memory cell, and a voltage of 0 V to an unselected word line. Selected memory by applying a voltage, applying a V PD (3 to 10V) voltage to the selected bit line, applying 0V to the bit line before the selected bit line, and applying a voltage of V PD to the bit line after the selected bit line Program data into the cell.
    Next, the V EG (-8 to -20 V) voltage is applied to the selected word line to erase the programmed data in the memory cell, and the voltage of V WELL (1 to 10 V) is applied to the P-well, and the unselected A voltage of 0 V is applied to the word line, and a voltage of V WELL is applied or floated to all bit lines to erase the memory cells.
    Finally, a voltage of V REF (3 to 6V) is applied to a selected word line to read data programmed into a memory cell, a voltage of 0V is applied to an unselected word line, and V READ (0.5 to 2V) to a selected bit line. The data programmed in the selected memory cell is read by applying a voltage of), applying 0V to the bit line before the selected bit line, and applying a voltage of V READ to the bit line after the selected bit line.
    1 is a layout view illustrating a conventional flash memory device.
    2 is a layout view illustrating a flash memory device according to the present invention.
    3A is a cross-sectional view of a silicon substrate having a triple well structure.
    3B to 3D are sectional views taken along the portion of FIG. 2;
    4 is a circuit diagram of a memory cell array in accordance with the present invention.
    Explanation of symbols on the main parts of the drawings
    1 and 11: field oxide films 2 and 12: floating gate
    3 and 13: control gate 4: contact portion
    5 and 15: source region 6 and 16: drain region
    14A: drain contact portion 14B: source contact portion
    20: silicon substrate 20A: N-well
    20B: P-well 21: tunnel oxide film
    22: dielectric film
    Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
    FIG. 2 is a layout view illustrating a flash memory device according to the present invention, in which a field oxide film 11 made of an octagonal shape having the same length of faces facing each other and a different length of neighboring surfaces in a source isolation region of a silicon substrate is shown. Are formed, and the field oxide films 11 are alternately arranged with other adjacent field oxide films 11. In order to form the field oxide film 11, a pad oxide film is formed on a silicon substrate having a triple well structure to a thickness of approximately 100 to 200 microseconds. The nitride film is deposited thereon, the nitride film of the portion where the field oxide film 11 is to be formed is etched, and a field oxide film 11 having a thickness of 3000 to 10000 kPa is formed by a thermal oxidation process.
    Next, a floating gate 12 is formed on the silicon substrate between the field oxide films 11 adjacent to each other, and the upper and lower portions partially overlap the field oxide film 11 and are electrically separated from the silicon substrate by the tunnel oxide film. The floating gate 12 is formed in a hexagon as shown in FIG. 2. Accordingly, it can be seen that the floating gate 12 has a large contact area with the control gate 13, thereby increasing the capacitor coupling ratio.
    Next, a control gate 13 is formed on the top of the field oxide layer 11 including the floating gate 12 horizontally adjacent to the floating gate 12 in the same width as the floating gate 12, and the floating gate 12 and the control gate ( 13) are electrically separated by a dielectric film. In addition, a source region 15 having a source contact portion 14B is formed in a silicon substrate in a portion surrounded by four adjacent field oxide films 11 and floating gates 12, and one side thereof is adjacent to the source region 15. A drain region 16 having a drain contact portion 14A is formed in the silicon substrate adjacent to the other side of the floating gate 12.
    Next, each part of the flash memory device will be described with reference to FIGS. 3B to 3D to facilitate understanding of the flash memory device of the present invention.
    Prior to this, the source, drain, and channel regions of the device are generally formed in the P-well in the silicon substrate. However, in the present invention, as shown in FIG. 3A, the P-well in the N-well 20A may have a triple well structure. A bias can be applied to 20B) to adopt a channel cancellation method. In order to form a silicon substrate having such a triple well structure, an oxide film (not shown) having a thickness of 250 to 350 GPa is grown on the silicon substrate, and then N-type impurity ions are implanted and diffused by a thermal process. 20A). Next, P-type impurity ions are implanted into the N-well 20A and diffused by a thermal process to form the P-well 20B. As a result, since the N-well 20A is surrounded by the P-well 20B and the N-well 20A is surrounded by the P-type silicon substrate 20, the channel erase method is possible by having a triple well structure. .
    FIG. 3B is a cross-sectional view of the flash memory device illustrated in FIG. 2 taken along the A1-A2 portion, and illustrates a state in which the source region 15 is formed in the silicon substrate 20 between adjacent field oxide films 11. do.
    FIG. 3C is a cross-sectional view of the flash memory device shown in FIG. 2 taken along the B1-B2 portion, and includes a tunnel oxide film 21 and a floating gate on a silicon substrate 20 between adjacent field oxide films 11. 12) shows a state in which the dielectric film 22 and the control gate 13 are stacked to form a gate electrode.
    3D is a cross-sectional view taken along the C1-C2 portion of the flash memory device shown in FIG. 2, showing the tunnel oxide film 21 on the silicon substrate 20 between the source region 15 and the drain region 16. The floating gate 12, dielectric film 22 and control gate 13 are stacked to form a gate electrode.
    The flash memory device configured as described above has four bits, that is, four memory cells share one source region 15 or drain region 16 and the source contact portion 14B of the source and drain regions 15 and 16. Or contact holes are formed in the drain contact portions 14A, respectively. Therefore, the size of the device is reduced because the area occupied by the contact holes as a whole is reduced compared to the conventional art. On the other hand, since the size of the field oxide film 11 and the floating gate 12 is increased compared to the prior art, the electrical insulation and operating characteristics between the devices are improved.
    In addition, the flash memory device configured as described above is represented by a circuit diagram as shown in FIG. 4. Next, an operation method for programming, erasing, and reading predetermined data into the memory cell of the portion A shown in FIG. 4 will be described. Same as
    First, V PG (8 to 20 V) is applied to the third word line WL3 and 0 V is applied to the other word lines, and V PD (3 to 10 V) and the first is applied to the third bit line BL3. And a voltage of 0 V to the second bit lines BL1 and BL2 and a voltage of V PD to the fourth and fifth bit lines BL4 and BL5, respectively. That is, when the n-th bit line BLn is selected, a voltage of 0 V is applied to the bit lines up to the i (in) th and a voltage of V PD is applied to the bit lines from the j (jn) th.
    Second, a voltage of V EG (-8 to -20 V) is applied to the third word line WL3 during an erase operation, and a voltage of V WELL (1 to 10 V) is applied to the P-well. At this time, a voltage of V WELL (1 to 10V) is applied or floated to the bit line.
    Third, V REF (3 to 6V) is applied to the third word line WL3 and 0 V is applied to the next word line during the read operation, and V READ (0.5 to 2V) is applied to the third bit line BL3. A voltage of 0 V is applied to the first and second bit lines BL1 and BL2 and V READ is applied to the fourth and fifth bit lines BL4 and BL5, respectively. That is, when the n-th bit line BLn is selected, a voltage of 0 V is applied to the bit lines up to the i (in) th and a voltage of V READ is applied to the bit lines from the j (jn) th.
    As described above, according to the present invention, four memory cells share a single source region or a drain region on a silicon substrate having a triple well structure, thereby reducing the area occupied by the contact hole, and also forming the floating gate in a hexagonal shape. Increasing the size of the floating gate has an excellent effect that can improve the integration and operation characteristics of the device.
    权利要求:
    Claims (12)
    [1" claim-type="Currently amended] In a flash memory device,
    A silicon substrate having a triple well structure,
    A field oxide film formed in each source isolation region of the silicon substrate;
    A floating gate formed on the silicon substrate between the field oxide films adjacent to each other, the upper and lower ends partially overlapping the field oxide film and electrically separated from the silicon substrate by a tunnel oxide film;
    A control gate including the floating gate formed in a horizontal direction and formed to have the same width as the floating gate and electrically separated from the floating gate by a dielectric film;
    A source region formed in the silicon substrate in a portion surrounded by the four adjacent field oxide films and the floating gate, and having a source contact portion;
    And a drain region formed in the silicon substrate adjacent to the other side of the floating gate adjacent to the source region and having a drain contact portion.
    [2" claim-type="Currently amended] The method of claim 1,
    The triple well is formed of an N-well formed in a P-type silicon substrate and a P-well formed in the P-well.
    [3" claim-type="Currently amended] The method of claim 1,
    And the field oxide layer is formed to a thickness of 3000 to 10000 GPa.
    [4" claim-type="Currently amended] The method according to claim 1 or 3,
    And the field oxide layer is formed in an octagonal shape.
    [5" claim-type="Currently amended] The method according to claim 1 or 3,
    And the field oxide film is alternately arranged with another adjacent field oxide film.
    [6" claim-type="Currently amended] The method of claim 1,
    And the floating gate has a hexagon shape.
    [7" claim-type="Currently amended] In the method of programming a flash memory device,
    Apply a V PG voltage to the selected word line, apply a voltage of 0 V to the unselected word line, apply a V PD voltage to the selected bit line, apply 0 V to the bit line before the selected bit line, and A method of programming a flash memory device, characterized in that data is programmed into a selected memory cell by applying a voltage of V PD to a bit line.
    [8" claim-type="Currently amended] The method of claim 7, wherein
    The V PG voltage is 8 to 20V, the V PG voltage is 3 to 10V program method of the flash memory device.
    [9" claim-type="Currently amended] In the erase method of a flash memory device having a triple well structure,
    Apply V EG voltage to the selected word line, V WELL to the P-well, 0 V to the unselected word line, and apply or float the voltage to V WELL on all bit lines. And erasing the memory cells.
    [10" claim-type="Currently amended] The method of claim 9,
    The V EG voltage is -8 to -20V, and the V WELL voltage is 1 to 10V erasing method of the flash memory device.
    [11" claim-type="Currently amended] In the method of reading a flash memory device,
    A voltage of V REF is applied to the selected word line, a voltage of 0 V is applied to the unselected word line, a voltage of V READ is applied to the selected bit line, 0 V is applied to the bit line before the selected bit line, and the selected bit line is applied. And reading data stored in a selected memory cell by applying a voltage of V READ to subsequent bit lines.
    [12" claim-type="Currently amended] The method of claim 11,
    The V REF voltage is 3 to 6V, the V READ voltage is 0.5 to 2V, the reading method of the flash memory device.
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    同族专利:
    公开号 | 公开日
    GB9727109D0|1998-02-25|
    GB2320810A8|1998-08-03|
    US5982671A|1999-11-09|
    GB2320810A|1998-07-01|
    KR100241523B1|2000-02-01|
    GB2320810B|2001-10-03|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    1996-12-28|Application filed by 김영환, 현대전자산업 주식회사
    1996-12-28|Priority to KR1019960074962A
    1998-09-25|Publication of KR19980055726A
    2000-02-01|Application granted
    2000-02-01|Publication of KR100241523B1
    优先权:
    申请号 | 申请日 | 专利标题
    KR1019960074962A|KR100241523B1|1996-12-28|1996-12-28|Flash memory device and its programming, erasing and reading method|
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